HI5714EVAL【PDF 1/11 页】EVALUATION PLATFORM HI5714

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Using the HI5714 Evaluation Board

Application Note

November 2002

AN9517.1

Author: Juan C. Garcia

Description

The HI5714 evaluation board was designed to easily allow a

user to evaluate the performance of the HI5714 8-bit

75 MSPS Analog-to-Digital converter (ADC). The board

includes clock driver circuitry, reference voltage generators,

two input options and a reconstruct DAC. A block diagram of

the evaluation board is shown in Figure 3.

HI5714 Theory of Operation

The HI5714 design utilizes a folding and interpolating

architecture. This architecture reduces the number of

comparators, reference taps, and latches in comparison to a

full parallel flash converter, and as a result reduces power

requirements, die size and cost. A full parallel 8-bit flash

converter requires 255 comparators, 255 references and

255 latches, while the HI5714 utilizes only 16 comparators,

16 references and 16 latches.

A folding A/D converter operates basically like a 2 step

Features

? HI5714 Analog to Digital Converter

? External Reference

? Two Analog Inputs: One AC Coupled, One DC Coupled

? Reconstruct DAC: HI5721

? Buffered Digital Outputs

The interpolation technique further reduces the number of

necessary amplifiers by using passive elements to derive the

remaining signals. Interpolation (as seen in Figure 2) takes

advantage of the overlap between two adjacent amplifiers

and uses resistor taps to fill in the gaps (thereby replacing

three out of every four amplifiers with resistors). Signal

distortion introduced by interpolation can be ignored as only

the zero crossing is of importance.

subranging converter by using 2 lower resolution converters

to do a course and subranged fine conversion. The major

difference in the folding technique is that the folding

V O

V 01

V 02

amplifiers are used to do the fine conversion in parallel

with the course conversion, where the fine and course

conversions are done in a sequential mode for a

V IN

conventional subranging converter. The folding architecture

V 2

V 3

V 4

uses only the folding amplifiers, voltage comparators, flip-

flops and decoding circuits. Sample and hold and DAC

circuits are not required.

A folding amplifier is a number of parallel differential pairs

with interconnected outputs as shown in Figure 1. The

folding ratio is the number of differential pairs used in the

amplifier, which is 16 for the HI5714. When compared to a

traditional straight flash architecture, one folding amplifier

with a folding ratio of 16 replaces 16 input comparators.

Assuming no interpolation were to be performed, the number

of folding amplifiers necessary to implement an 8-bit

conversion (using a folding ratio of 16) would be DC at 16.

V CC

FIGURE 2. INTERPOLATED AMPLIFIER OUTPUTS

As stated earlier in this section, the HI5714 uses a folding

ratio of 16 (16 latched comparators) with an interpolation

ratio of 4 (4 folding amplifiers). These 16 latched

comparators in turn are decoded into 32 ROM enables to

provide the 5 LSBs of the converter. There are 8 subranging

sections of the input voltage range which perform the coarse

conversion and provide the 3 MSBs of the device.

The bias current generator is based on a simple band gap

reference which provides a typical variation of 1% over the

full temperature range.

The operation of the part is depicted in the timing diagram in

Figure 4. There is a 1 cycle clock delay from the analog input

V 1

V A

V 2

V B

V 3

sampling point to the corresponding digital output data.

V IN

FIGURE 1. FOLDING AMPLIFIER WITH A FOLDING RATIO OF 2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

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